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<div class="header">
  <div class="summary">
<a href="#func-members">Functions</a>  </div>
  <div class="headertitle">
<div class="title">SIO Functions<div class="ingroups"><a class="el" href="group__group__gpio.html">GPIO         (General Purpose Input Output)</a> &raquo; <a class="el" href="group__group__gpio__functions.html">Functions</a></div></div>  </div>
</div><!--header-->
<div class="contents">
<a name="details" id="details"></a><h2 class="groupheader">General Description</h2>
<table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="func-members"></a>
Functions</h2></td></tr>
<tr class="memitem:ga0d52bed24a328582918b5493c79f10cd"><td class="memItemLeft" align="right" valign="top">__STATIC_INLINE void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__gpio__functions__sio.html#ga0d52bed24a328582918b5493c79f10cd">Cy_GPIO_SetVregEn</a> (<a class="el" href="struct_g_p_i_o___p_r_t___type.html">GPIO_PRT_Type</a> *base, uint32_t pinNum, uint32_t value)</td></tr>
<tr class="memdesc:ga0d52bed24a328582918b5493c79f10cd"><td class="mdescLeft">&#160;</td><td class="mdescRight">Configures the SIO pin pair output buffer regulation mode.  <a href="#ga0d52bed24a328582918b5493c79f10cd">More...</a><br /></td></tr>
<tr class="separator:ga0d52bed24a328582918b5493c79f10cd"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga8189444fcd0644bec2362be0a9d70b2d"><td class="memItemLeft" align="right" valign="top">__STATIC_INLINE uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__gpio__functions__sio.html#ga8189444fcd0644bec2362be0a9d70b2d">Cy_GPIO_GetVregEn</a> (<a class="el" href="struct_g_p_i_o___p_r_t___type.html">GPIO_PRT_Type</a> *base, uint32_t pinNum)</td></tr>
<tr class="memdesc:ga8189444fcd0644bec2362be0a9d70b2d"><td class="mdescLeft">&#160;</td><td class="mdescRight">Returns the SIO pin pair output buffer regulation mode.  <a href="#ga8189444fcd0644bec2362be0a9d70b2d">More...</a><br /></td></tr>
<tr class="separator:ga8189444fcd0644bec2362be0a9d70b2d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga68cd1291bf4d0878e6155a6f3d3f0d48"><td class="memItemLeft" align="right" valign="top">__STATIC_INLINE void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__gpio__functions__sio.html#ga68cd1291bf4d0878e6155a6f3d3f0d48">Cy_GPIO_SetIbufMode</a> (<a class="el" href="struct_g_p_i_o___p_r_t___type.html">GPIO_PRT_Type</a> *base, uint32_t pinNum, uint32_t value)</td></tr>
<tr class="memdesc:ga68cd1291bf4d0878e6155a6f3d3f0d48"><td class="mdescLeft">&#160;</td><td class="mdescRight">Configures the SIO pin pair input buffer mode.  <a href="#ga68cd1291bf4d0878e6155a6f3d3f0d48">More...</a><br /></td></tr>
<tr class="separator:ga68cd1291bf4d0878e6155a6f3d3f0d48"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaee7a996f940d1f4da6783a5704e5ea8a"><td class="memItemLeft" align="right" valign="top">__STATIC_INLINE uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__gpio__functions__sio.html#gaee7a996f940d1f4da6783a5704e5ea8a">Cy_GPIO_GetIbufMode</a> (<a class="el" href="struct_g_p_i_o___p_r_t___type.html">GPIO_PRT_Type</a> *base, uint32_t pinNum)</td></tr>
<tr class="memdesc:gaee7a996f940d1f4da6783a5704e5ea8a"><td class="mdescLeft">&#160;</td><td class="mdescRight">Returns the SIO pin pair input buffer mode.  <a href="#gaee7a996f940d1f4da6783a5704e5ea8a">More...</a><br /></td></tr>
<tr class="separator:gaee7a996f940d1f4da6783a5704e5ea8a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaa737d4b37f0480062ccbc6c484feab87"><td class="memItemLeft" align="right" valign="top">__STATIC_INLINE void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__gpio__functions__sio.html#gaa737d4b37f0480062ccbc6c484feab87">Cy_GPIO_SetVtripSel</a> (<a class="el" href="struct_g_p_i_o___p_r_t___type.html">GPIO_PRT_Type</a> *base, uint32_t pinNum, uint32_t value)</td></tr>
<tr class="memdesc:gaa737d4b37f0480062ccbc6c484feab87"><td class="mdescLeft">&#160;</td><td class="mdescRight">Configures the SIO pin pair input buffer trip point.  <a href="#gaa737d4b37f0480062ccbc6c484feab87">More...</a><br /></td></tr>
<tr class="separator:gaa737d4b37f0480062ccbc6c484feab87"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga22d9f3a603348606519ea8cd3a192eff"><td class="memItemLeft" align="right" valign="top">__STATIC_INLINE uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__gpio__functions__sio.html#ga22d9f3a603348606519ea8cd3a192eff">Cy_GPIO_GetVtripSel</a> (<a class="el" href="struct_g_p_i_o___p_r_t___type.html">GPIO_PRT_Type</a> *base, uint32_t pinNum)</td></tr>
<tr class="memdesc:ga22d9f3a603348606519ea8cd3a192eff"><td class="mdescLeft">&#160;</td><td class="mdescRight">Returns the SIO pin pair input buffer trip point.  <a href="#ga22d9f3a603348606519ea8cd3a192eff">More...</a><br /></td></tr>
<tr class="separator:ga22d9f3a603348606519ea8cd3a192eff"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gad57f3f01fb4fee362bf8379f265352a5"><td class="memItemLeft" align="right" valign="top">__STATIC_INLINE void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__gpio__functions__sio.html#gad57f3f01fb4fee362bf8379f265352a5">Cy_GPIO_SetVrefSel</a> (<a class="el" href="struct_g_p_i_o___p_r_t___type.html">GPIO_PRT_Type</a> *base, uint32_t pinNum, uint32_t value)</td></tr>
<tr class="memdesc:gad57f3f01fb4fee362bf8379f265352a5"><td class="mdescLeft">&#160;</td><td class="mdescRight">Configures the SIO reference voltage for the input buffer trip point.  <a href="#gad57f3f01fb4fee362bf8379f265352a5">More...</a><br /></td></tr>
<tr class="separator:gad57f3f01fb4fee362bf8379f265352a5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga8f3e4432afbec7485dffe1606dc6233a"><td class="memItemLeft" align="right" valign="top">__STATIC_INLINE uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__gpio__functions__sio.html#ga8f3e4432afbec7485dffe1606dc6233a">Cy_GPIO_GetVrefSel</a> (<a class="el" href="struct_g_p_i_o___p_r_t___type.html">GPIO_PRT_Type</a> *base, uint32_t pinNum)</td></tr>
<tr class="memdesc:ga8f3e4432afbec7485dffe1606dc6233a"><td class="mdescLeft">&#160;</td><td class="mdescRight">Returns the SIO reference voltage for the input buffer trip point.  <a href="#ga8f3e4432afbec7485dffe1606dc6233a">More...</a><br /></td></tr>
<tr class="separator:ga8f3e4432afbec7485dffe1606dc6233a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gae5ec56c5d9eb48cb589d206559e2c7fe"><td class="memItemLeft" align="right" valign="top">__STATIC_INLINE void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__gpio__functions__sio.html#gae5ec56c5d9eb48cb589d206559e2c7fe">Cy_GPIO_SetVohSel</a> (<a class="el" href="struct_g_p_i_o___p_r_t___type.html">GPIO_PRT_Type</a> *base, uint32_t pinNum, uint32_t value)</td></tr>
<tr class="memdesc:gae5ec56c5d9eb48cb589d206559e2c7fe"><td class="mdescLeft">&#160;</td><td class="mdescRight">Configures the regulated output reference multiplier for the SIO pin pair.  <a href="#gae5ec56c5d9eb48cb589d206559e2c7fe">More...</a><br /></td></tr>
<tr class="separator:gae5ec56c5d9eb48cb589d206559e2c7fe"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga304ce3205081a7a29268d3c32bf3b95a"><td class="memItemLeft" align="right" valign="top">__STATIC_INLINE uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__gpio__functions__sio.html#ga304ce3205081a7a29268d3c32bf3b95a">Cy_GPIO_GetVohSel</a> (<a class="el" href="struct_g_p_i_o___p_r_t___type.html">GPIO_PRT_Type</a> *base, uint32_t pinNum)</td></tr>
<tr class="memdesc:ga304ce3205081a7a29268d3c32bf3b95a"><td class="mdescLeft">&#160;</td><td class="mdescRight">Returns the regulated output reference multiplier for the SIO pin pair.  <a href="#ga304ce3205081a7a29268d3c32bf3b95a">More...</a><br /></td></tr>
<tr class="separator:ga304ce3205081a7a29268d3c32bf3b95a"><td class="memSeparator" colspan="2">&#160;</td></tr>
</table>
<h2 class="groupheader">Function Documentation</h2>
<a id="ga0d52bed24a328582918b5493c79f10cd"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga0d52bed24a328582918b5493c79f10cd">&#9670;&nbsp;</a></span>Cy_GPIO_SetVregEn()</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">__STATIC_INLINE void Cy_GPIO_SetVregEn </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_g_p_i_o___p_r_t___type.html">GPIO_PRT_Type</a> *&#160;</td>
          <td class="paramname"><em>base</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">uint32_t&#160;</td>
          <td class="paramname"><em>pinNum</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">uint32_t&#160;</td>
          <td class="paramname"><em>value</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Configures the SIO pin pair output buffer regulation mode. </p>
<p>Note that this function has no effect on non-SIO pins.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">base</td><td>Pointer to the pin's port register base address</td></tr>
    <tr><td class="paramname">pinNum</td><td>Position of the pin bit-field within the port register</td></tr>
    <tr><td class="paramname">value</td><td>SIO pair output buffer regulator mode. Options are detailed in <a class="el" href="group__group__gpio__sio_vreg.html">SIO output buffer mode</a> macros</td></tr>
  </table>
  </dd>
</dl>
<dl class="section note"><dt>Note</dt><dd>This function modifies a port register in a read-modify-write operation. It is not thread safe as the resource is shared among multiple pins on a port.</dd></dl>
<dl class="section user"><dt>Function Usage</dt><dd><div class="fragment"><div class="line"></div><div class="line">    <span class="comment">/* Scenario: Assume P0.3 is an SIO pin and that it is paired with P0.2.</span></div><div class="line"><span class="comment">                 Both pins are configured as output pins. The output (driven)</span></div><div class="line"><span class="comment">                 signals on P0.2 and P0.3 need to be at a regulated voltage</span></div><div class="line"><span class="comment">                 based on Voh and VRef selection. */</span></div><div class="line"></div><div class="line">    <span class="comment">/* Get the output buffer regulation mode of P0.2/P0.3 pair */</span></div><div class="line">    <span class="keywordflow">if</span>(<a class="code" href="group__group__gpio__sio_vreg.html#ga4a90fae5df22762b5aa60b5b4e9bea85">CY_SIO_VREG_UNREGULATED</a> == <a class="code" href="group__group__gpio__functions__sio.html#ga8189444fcd0644bec2362be0a9d70b2d">Cy_GPIO_GetVregEn</a>(P0_3_PORT, P0_3_NUM))</div><div class="line">    {</div><div class="line">        <span class="comment">/* Set the output buffer to be regulated on the P0.2/P0.3 SIO pair */</span></div><div class="line">        <a class="code" href="group__group__gpio__functions__sio.html#ga0d52bed24a328582918b5493c79f10cd">Cy_GPIO_SetVregEn</a>(P0_3_PORT, P0_3_NUM, <a class="code" href="group__group__gpio__sio_vreg.html#ga593d5f4da327d288ca55cadc29aa7c43">CY_SIO_VREG_REGULATED</a>);</div><div class="line">    }</div><div class="line"></div></div><!-- fragment --></dd></dl>

</div>
</div>
<a id="ga8189444fcd0644bec2362be0a9d70b2d"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga8189444fcd0644bec2362be0a9d70b2d">&#9670;&nbsp;</a></span>Cy_GPIO_GetVregEn()</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">__STATIC_INLINE uint32_t Cy_GPIO_GetVregEn </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_g_p_i_o___p_r_t___type.html">GPIO_PRT_Type</a> *&#160;</td>
          <td class="paramname"><em>base</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">uint32_t&#160;</td>
          <td class="paramname"><em>pinNum</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Returns the SIO pin pair output buffer regulation mode. </p>
<p>Note that this function has no effect on non-SIO pins.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">base</td><td>Pointer to the pin's port register base address</td></tr>
    <tr><td class="paramname">pinNum</td><td>Position of the pin bit-field within the port register</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>SIO pair output buffer regulator mode. Options are detailed in <a class="el" href="group__group__gpio__sio_vreg.html">SIO output buffer mode</a> macros</dd></dl>
<dl class="section user"><dt>Function Usage</dt><dd><div class="fragment"><div class="line"></div><div class="line">    <span class="comment">/* Scenario: Assume P0.3 is an SIO pin and that it is paired with P0.2.</span></div><div class="line"><span class="comment">                 Both pins are configured as output pins. The output (driven)</span></div><div class="line"><span class="comment">                 signals on P0.2 and P0.3 need to be at a regulated voltage</span></div><div class="line"><span class="comment">                 based on Voh and VRef selection. */</span></div><div class="line"></div><div class="line">    <span class="comment">/* Get the output buffer regulation mode of P0.2/P0.3 pair */</span></div><div class="line">    <span class="keywordflow">if</span>(<a class="code" href="group__group__gpio__sio_vreg.html#ga4a90fae5df22762b5aa60b5b4e9bea85">CY_SIO_VREG_UNREGULATED</a> == <a class="code" href="group__group__gpio__functions__sio.html#ga8189444fcd0644bec2362be0a9d70b2d">Cy_GPIO_GetVregEn</a>(P0_3_PORT, P0_3_NUM))</div><div class="line">    {</div><div class="line">        <span class="comment">/* Set the output buffer to be regulated on the P0.2/P0.3 SIO pair */</span></div><div class="line">        <a class="code" href="group__group__gpio__functions__sio.html#ga0d52bed24a328582918b5493c79f10cd">Cy_GPIO_SetVregEn</a>(P0_3_PORT, P0_3_NUM, <a class="code" href="group__group__gpio__sio_vreg.html#ga593d5f4da327d288ca55cadc29aa7c43">CY_SIO_VREG_REGULATED</a>);</div><div class="line">    }</div><div class="line"></div></div><!-- fragment --></dd></dl>

</div>
</div>
<a id="ga68cd1291bf4d0878e6155a6f3d3f0d48"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga68cd1291bf4d0878e6155a6f3d3f0d48">&#9670;&nbsp;</a></span>Cy_GPIO_SetIbufMode()</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">__STATIC_INLINE void Cy_GPIO_SetIbufMode </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_g_p_i_o___p_r_t___type.html">GPIO_PRT_Type</a> *&#160;</td>
          <td class="paramname"><em>base</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">uint32_t&#160;</td>
          <td class="paramname"><em>pinNum</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">uint32_t&#160;</td>
          <td class="paramname"><em>value</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Configures the SIO pin pair input buffer mode. </p>
<p>Note that this function has no effect on non-SIO pins.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">base</td><td>Pointer to the pin's port register base address</td></tr>
    <tr><td class="paramname">pinNum</td><td>Position of the pin bit-field within the port register</td></tr>
    <tr><td class="paramname">value</td><td>SIO pair input buffer mode. Options are detailed in <a class="el" href="group__group__gpio__sio_ibuf.html">SIO input buffer mode</a> macros</td></tr>
  </table>
  </dd>
</dl>
<dl class="section note"><dt>Note</dt><dd>This function modifies a port register in a read-modify-write operation. It is not thread safe as the resource is shared among multiple pins on a port.</dd></dl>
<dl class="section user"><dt>Function Usage</dt><dd><div class="fragment"><div class="line"></div><div class="line">    <span class="comment">/* Scenario: Assume P0.3 is an SIO pin and that it is paired with P0.2.</span></div><div class="line"><span class="comment">                 Both pins are configured as input pins. The input signals</span></div><div class="line"><span class="comment">                 on P0.2 and P0.3 need to be interpreted as logic 0 or 1</span></div><div class="line"><span class="comment">                 depending on the chosen SIO vtrip point. */</span></div><div class="line"></div><div class="line">    <span class="comment">/* Get the input buffer mode of P0.2/P0.3 pair */</span></div><div class="line">    <span class="keywordflow">if</span>(<a class="code" href="group__group__gpio__sio_ibuf.html#ga034ddc1e49da85e6b6d8841a3e90dfce">CY_SIO_IBUF_SINGLEENDED</a> == <a class="code" href="group__group__gpio__functions__sio.html#gaee7a996f940d1f4da6783a5704e5ea8a">Cy_GPIO_GetIbufMode</a>(P0_3_PORT, P0_3_NUM))</div><div class="line">    {</div><div class="line">        <span class="comment">/* Set the input buffer to be differential on the P0.2/P0.3 SIO pair */</span></div><div class="line">        <a class="code" href="group__group__gpio__functions__sio.html#ga68cd1291bf4d0878e6155a6f3d3f0d48">Cy_GPIO_SetIbufMode</a>(P0_3_PORT, P0_3_NUM, <a class="code" href="group__group__gpio__sio_ibuf.html#ga6850dffbb80666798735b2914c0aa4d0">CY_SIO_IBUF_DIFFERENTIAL</a>);</div><div class="line">    }</div><div class="line"></div></div><!-- fragment --></dd></dl>

</div>
</div>
<a id="gaee7a996f940d1f4da6783a5704e5ea8a"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gaee7a996f940d1f4da6783a5704e5ea8a">&#9670;&nbsp;</a></span>Cy_GPIO_GetIbufMode()</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">__STATIC_INLINE uint32_t Cy_GPIO_GetIbufMode </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_g_p_i_o___p_r_t___type.html">GPIO_PRT_Type</a> *&#160;</td>
          <td class="paramname"><em>base</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">uint32_t&#160;</td>
          <td class="paramname"><em>pinNum</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Returns the SIO pin pair input buffer mode. </p>
<p>Note that this function has no effect on non-SIO pins.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">base</td><td>Pointer to the pin's port register base address</td></tr>
    <tr><td class="paramname">pinNum</td><td>Position of the pin bit-field within the port register</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>SIO pair input buffer mode. Options are detailed in <a class="el" href="group__group__gpio__sio_ibuf.html">SIO input buffer mode</a> macros</dd></dl>
<dl class="section user"><dt>Function Usage</dt><dd><div class="fragment"><div class="line"></div><div class="line">    <span class="comment">/* Scenario: Assume P0.3 is an SIO pin and that it is paired with P0.2.</span></div><div class="line"><span class="comment">                 Both pins are configured as input pins. The input signals</span></div><div class="line"><span class="comment">                 on P0.2 and P0.3 need to be interpreted as logic 0 or 1</span></div><div class="line"><span class="comment">                 depending on the chosen SIO vtrip point. */</span></div><div class="line"></div><div class="line">    <span class="comment">/* Get the input buffer mode of P0.2/P0.3 pair */</span></div><div class="line">    <span class="keywordflow">if</span>(<a class="code" href="group__group__gpio__sio_ibuf.html#ga034ddc1e49da85e6b6d8841a3e90dfce">CY_SIO_IBUF_SINGLEENDED</a> == <a class="code" href="group__group__gpio__functions__sio.html#gaee7a996f940d1f4da6783a5704e5ea8a">Cy_GPIO_GetIbufMode</a>(P0_3_PORT, P0_3_NUM))</div><div class="line">    {</div><div class="line">        <span class="comment">/* Set the input buffer to be differential on the P0.2/P0.3 SIO pair */</span></div><div class="line">        <a class="code" href="group__group__gpio__functions__sio.html#ga68cd1291bf4d0878e6155a6f3d3f0d48">Cy_GPIO_SetIbufMode</a>(P0_3_PORT, P0_3_NUM, <a class="code" href="group__group__gpio__sio_ibuf.html#ga6850dffbb80666798735b2914c0aa4d0">CY_SIO_IBUF_DIFFERENTIAL</a>);</div><div class="line">    }</div><div class="line"></div></div><!-- fragment --></dd></dl>

</div>
</div>
<a id="gaa737d4b37f0480062ccbc6c484feab87"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gaa737d4b37f0480062ccbc6c484feab87">&#9670;&nbsp;</a></span>Cy_GPIO_SetVtripSel()</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">__STATIC_INLINE void Cy_GPIO_SetVtripSel </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_g_p_i_o___p_r_t___type.html">GPIO_PRT_Type</a> *&#160;</td>
          <td class="paramname"><em>base</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">uint32_t&#160;</td>
          <td class="paramname"><em>pinNum</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">uint32_t&#160;</td>
          <td class="paramname"><em>value</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Configures the SIO pin pair input buffer trip point. </p>
<p>Note that this function has no effect on non-SIO pins.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">base</td><td>Pointer to the pin's port register base address</td></tr>
    <tr><td class="paramname">pinNum</td><td>Position of the pin bit-field within the port register</td></tr>
    <tr><td class="paramname">value</td><td>SIO pair input buffer trip point. Options are detailed in <a class="el" href="group__group__gpio__sio_vtrip.html">SIO input buffer trip-point</a> macros</td></tr>
  </table>
  </dd>
</dl>
<dl class="section note"><dt>Note</dt><dd>This function modifies a port register in a read-modify-write operation. It is not thread safe as the resource is shared among multiple pins on a port.</dd></dl>
<dl class="section user"><dt>Function Usage</dt><dd><div class="fragment"><div class="line"></div><div class="line">    <span class="comment">/* Scenario: Assume P0.3 is an SIO pin and that it is paired with P0.2.</span></div><div class="line"><span class="comment">                 Both pins are configured as input pins. The input signals</span></div><div class="line"><span class="comment">                 on P0.2 and P0.3 need to be interpreted as logic 0 or 1 at</span></div><div class="line"><span class="comment">                 0.5 x VDDIO threshold. */</span></div><div class="line"></div><div class="line">    <span class="comment">/* Set the input buffer to be differential on the P0.2/P0.3 SIO pair */</span></div><div class="line">    <a class="code" href="group__group__gpio__functions__sio.html#ga68cd1291bf4d0878e6155a6f3d3f0d48">Cy_GPIO_SetIbufMode</a>(P0_3_PORT, P0_3_NUM, <a class="code" href="group__group__gpio__sio_ibuf.html#ga6850dffbb80666798735b2914c0aa4d0">CY_SIO_IBUF_DIFFERENTIAL</a>);</div><div class="line"></div><div class="line">    <span class="comment">/* Choose VREF to be sourced from VDDIO (pin ref) */</span></div><div class="line">    <a class="code" href="group__group__gpio__functions__sio.html#gad57f3f01fb4fee362bf8379f265352a5">Cy_GPIO_SetVrefSel</a>(P0_3_PORT, P0_3_NUM, <a class="code" href="group__group__gpio__sio_vref.html#ga7068729049c6c4d4b9a5bc5b35fd5cf8">CY_SIO_VREF_PINREF</a>);</div><div class="line"></div><div class="line">    <span class="comment">/* Get the input buffer trip-point of P0.2/P0.3 pair */</span></div><div class="line">    <span class="keywordflow">if</span>(<a class="code" href="group__group__gpio__sio_vtrip.html#ga604bd3b5b4bda6fd88a434e7df3c55aa">CY_SIO_VTRIP_CMOS</a> == <a class="code" href="group__group__gpio__functions__sio.html#ga22d9f3a603348606519ea8cd3a192eff">Cy_GPIO_GetVtripSel</a>(P0_3_PORT, P0_3_NUM))</div><div class="line">    {</div><div class="line">        <span class="comment">/* Set the input buffer trip-point to 0.5 x VDDIO on the P0.2/P0.3 SIO pair */</span></div><div class="line">        <a class="code" href="group__group__gpio__functions__sio.html#gaa737d4b37f0480062ccbc6c484feab87">Cy_GPIO_SetVtripSel</a>(P0_3_PORT, P0_3_NUM, <a class="code" href="group__group__gpio__sio_vtrip.html#ga3b4be6e3a866fde6dc4fa815f1f1a65c">CY_SIO_VTRIP_0_5VDDIO_0_5VOH</a>);</div><div class="line">    }</div><div class="line"></div></div><!-- fragment --></dd></dl>

</div>
</div>
<a id="ga22d9f3a603348606519ea8cd3a192eff"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga22d9f3a603348606519ea8cd3a192eff">&#9670;&nbsp;</a></span>Cy_GPIO_GetVtripSel()</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">__STATIC_INLINE uint32_t Cy_GPIO_GetVtripSel </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_g_p_i_o___p_r_t___type.html">GPIO_PRT_Type</a> *&#160;</td>
          <td class="paramname"><em>base</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">uint32_t&#160;</td>
          <td class="paramname"><em>pinNum</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Returns the SIO pin pair input buffer trip point. </p>
<p>Note that this function has no effect on non-SIO pins.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">base</td><td>Pointer to the pin's port register base address</td></tr>
    <tr><td class="paramname">pinNum</td><td>Position of the pin bit-field within the port register</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>SIO pair input buffer trip point. Options are detailed in <a class="el" href="group__group__gpio__sio_vtrip.html">SIO input buffer trip-point</a> macros</dd></dl>
<dl class="section user"><dt>Function Usage</dt><dd><div class="fragment"><div class="line"></div><div class="line">    <span class="comment">/* Scenario: Assume P0.3 is an SIO pin and that it is paired with P0.2.</span></div><div class="line"><span class="comment">                 Both pins are configured as input pins. The input signals</span></div><div class="line"><span class="comment">                 on P0.2 and P0.3 need to be interpreted as logic 0 or 1 at</span></div><div class="line"><span class="comment">                 0.5 x VDDIO threshold. */</span></div><div class="line"></div><div class="line">    <span class="comment">/* Set the input buffer to be differential on the P0.2/P0.3 SIO pair */</span></div><div class="line">    <a class="code" href="group__group__gpio__functions__sio.html#ga68cd1291bf4d0878e6155a6f3d3f0d48">Cy_GPIO_SetIbufMode</a>(P0_3_PORT, P0_3_NUM, <a class="code" href="group__group__gpio__sio_ibuf.html#ga6850dffbb80666798735b2914c0aa4d0">CY_SIO_IBUF_DIFFERENTIAL</a>);</div><div class="line"></div><div class="line">    <span class="comment">/* Choose VREF to be sourced from VDDIO (pin ref) */</span></div><div class="line">    <a class="code" href="group__group__gpio__functions__sio.html#gad57f3f01fb4fee362bf8379f265352a5">Cy_GPIO_SetVrefSel</a>(P0_3_PORT, P0_3_NUM, <a class="code" href="group__group__gpio__sio_vref.html#ga7068729049c6c4d4b9a5bc5b35fd5cf8">CY_SIO_VREF_PINREF</a>);</div><div class="line"></div><div class="line">    <span class="comment">/* Get the input buffer trip-point of P0.2/P0.3 pair */</span></div><div class="line">    <span class="keywordflow">if</span>(<a class="code" href="group__group__gpio__sio_vtrip.html#ga604bd3b5b4bda6fd88a434e7df3c55aa">CY_SIO_VTRIP_CMOS</a> == <a class="code" href="group__group__gpio__functions__sio.html#ga22d9f3a603348606519ea8cd3a192eff">Cy_GPIO_GetVtripSel</a>(P0_3_PORT, P0_3_NUM))</div><div class="line">    {</div><div class="line">        <span class="comment">/* Set the input buffer trip-point to 0.5 x VDDIO on the P0.2/P0.3 SIO pair */</span></div><div class="line">        <a class="code" href="group__group__gpio__functions__sio.html#gaa737d4b37f0480062ccbc6c484feab87">Cy_GPIO_SetVtripSel</a>(P0_3_PORT, P0_3_NUM, <a class="code" href="group__group__gpio__sio_vtrip.html#ga3b4be6e3a866fde6dc4fa815f1f1a65c">CY_SIO_VTRIP_0_5VDDIO_0_5VOH</a>);</div><div class="line">    }</div><div class="line"></div></div><!-- fragment --></dd></dl>

</div>
</div>
<a id="gad57f3f01fb4fee362bf8379f265352a5"></a>
<h2 class="memtitle"><span class="permalink"><a href="#gad57f3f01fb4fee362bf8379f265352a5">&#9670;&nbsp;</a></span>Cy_GPIO_SetVrefSel()</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">__STATIC_INLINE void Cy_GPIO_SetVrefSel </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_g_p_i_o___p_r_t___type.html">GPIO_PRT_Type</a> *&#160;</td>
          <td class="paramname"><em>base</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">uint32_t&#160;</td>
          <td class="paramname"><em>pinNum</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">uint32_t&#160;</td>
          <td class="paramname"><em>value</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Configures the SIO reference voltage for the input buffer trip point. </p>
<p>Note that this function has no effect on non-SIO pins.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">base</td><td>Pointer to the pin's port register base address</td></tr>
    <tr><td class="paramname">pinNum</td><td>Position of the pin bit-field within the port register</td></tr>
    <tr><td class="paramname">value</td><td>SIO pair reference voltage. Options are detailed in <a class="el" href="group__group__gpio__sio_vref.html">SIO reference voltage for input buffer trip-point</a> macros</td></tr>
  </table>
  </dd>
</dl>
<dl class="section note"><dt>Note</dt><dd>This function modifies a port register in a read-modify-write operation. It is not thread safe as the resource is shared among multiple pins on a port.</dd></dl>
<dl class="section user"><dt>Function Usage</dt><dd><div class="fragment"><div class="line"></div><div class="line">    <span class="comment">/* Scenario: Assume P0.3 is an SIO pin and that it is paired with P0.2.</span></div><div class="line"><span class="comment">                 Both pins are configured as input pins. The input signals</span></div><div class="line"><span class="comment">                 on P0.2 and P0.3 need to be interpreted as logic 0 or 1 at</span></div><div class="line"><span class="comment">                 1.25 x 1.2V threshold. */</span></div><div class="line"></div><div class="line">    <span class="comment">/* Set the input buffer to be differential on the P0.2/P0.3 SIO pair */</span></div><div class="line">    <a class="code" href="group__group__gpio__functions__sio.html#ga68cd1291bf4d0878e6155a6f3d3f0d48">Cy_GPIO_SetIbufMode</a>(P0_3_PORT, P0_3_NUM, <a class="code" href="group__group__gpio__sio_ibuf.html#ga6850dffbb80666798735b2914c0aa4d0">CY_SIO_IBUF_DIFFERENTIAL</a>);</div><div class="line"></div><div class="line">    <span class="comment">/* Set the input buffer trip-point to 0.5 x VOH on the P0.2/P0.3 SIO pair */</span></div><div class="line">    <a class="code" href="group__group__gpio__functions__sio.html#gaa737d4b37f0480062ccbc6c484feab87">Cy_GPIO_SetVtripSel</a>(P0_3_PORT, P0_3_NUM, <a class="code" href="group__group__gpio__sio_vtrip.html#ga3b4be6e3a866fde6dc4fa815f1f1a65c">CY_SIO_VTRIP_0_5VDDIO_0_5VOH</a>);</div><div class="line"></div><div class="line">    <span class="comment">/* Set the regulated input buffer trip point multiplier to 1.25 x VRef */</span></div><div class="line">    <a class="code" href="group__group__gpio__functions__sio.html#gae5ec56c5d9eb48cb589d206559e2c7fe">Cy_GPIO_SetVohSel</a>(P0_3_PORT, P0_3_NUM, <a class="code" href="group__group__gpio__sio_voh.html#ga82a402925161b65fee4e301734b4d42e">CY_SIO_VOH_1_25</a>);</div><div class="line"></div><div class="line">    <span class="comment">/* Get the reference voltage of P0.2/P0.3 pair */</span></div><div class="line">    <span class="keywordflow">if</span>(<a class="code" href="group__group__gpio__sio_vref.html#ga7068729049c6c4d4b9a5bc5b35fd5cf8">CY_SIO_VREF_PINREF</a> == <a class="code" href="group__group__gpio__functions__sio.html#ga8f3e4432afbec7485dffe1606dc6233a">Cy_GPIO_GetVrefSel</a>(P0_3_PORT, P0_3_NUM))</div><div class="line">    {</div><div class="line">        <span class="comment">/* Set the reference voltage to 1.2V SRSS internal reference on the P0.2/P0.3 SIO pair */</span></div><div class="line">        <a class="code" href="group__group__gpio__functions__sio.html#gad57f3f01fb4fee362bf8379f265352a5">Cy_GPIO_SetVrefSel</a>(P0_3_PORT, P0_3_NUM, <a class="code" href="group__group__gpio__sio_vref.html#gaa5c0ec7f4e60d65f581e5f6544b76223">CY_SIO_VREF_1_2V</a>);</div><div class="line">    }</div><div class="line"></div></div><!-- fragment --></dd></dl>

</div>
</div>
<a id="ga8f3e4432afbec7485dffe1606dc6233a"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga8f3e4432afbec7485dffe1606dc6233a">&#9670;&nbsp;</a></span>Cy_GPIO_GetVrefSel()</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">__STATIC_INLINE uint32_t Cy_GPIO_GetVrefSel </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_g_p_i_o___p_r_t___type.html">GPIO_PRT_Type</a> *&#160;</td>
          <td class="paramname"><em>base</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">uint32_t&#160;</td>
          <td class="paramname"><em>pinNum</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Returns the SIO reference voltage for the input buffer trip point. </p>
<p>Note that this function has no effect on non-SIO pins.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">base</td><td>Pointer to the pin's port register base address</td></tr>
    <tr><td class="paramname">pinNum</td><td>Position of the pin bit-field within the port register</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>SIO pair reference voltage. Options are detailed in <a class="el" href="group__group__gpio__sio_vref.html">SIO reference voltage for input buffer trip-point</a> macros</dd></dl>
<dl class="section user"><dt>Function Usage</dt><dd><div class="fragment"><div class="line"></div><div class="line">    <span class="comment">/* Scenario: Assume P0.3 is an SIO pin and that it is paired with P0.2.</span></div><div class="line"><span class="comment">                 Both pins are configured as input pins. The input signals</span></div><div class="line"><span class="comment">                 on P0.2 and P0.3 need to be interpreted as logic 0 or 1 at</span></div><div class="line"><span class="comment">                 1.25 x 1.2V threshold. */</span></div><div class="line"></div><div class="line">    <span class="comment">/* Set the input buffer to be differential on the P0.2/P0.3 SIO pair */</span></div><div class="line">    <a class="code" href="group__group__gpio__functions__sio.html#ga68cd1291bf4d0878e6155a6f3d3f0d48">Cy_GPIO_SetIbufMode</a>(P0_3_PORT, P0_3_NUM, <a class="code" href="group__group__gpio__sio_ibuf.html#ga6850dffbb80666798735b2914c0aa4d0">CY_SIO_IBUF_DIFFERENTIAL</a>);</div><div class="line"></div><div class="line">    <span class="comment">/* Set the input buffer trip-point to 0.5 x VOH on the P0.2/P0.3 SIO pair */</span></div><div class="line">    <a class="code" href="group__group__gpio__functions__sio.html#gaa737d4b37f0480062ccbc6c484feab87">Cy_GPIO_SetVtripSel</a>(P0_3_PORT, P0_3_NUM, <a class="code" href="group__group__gpio__sio_vtrip.html#ga3b4be6e3a866fde6dc4fa815f1f1a65c">CY_SIO_VTRIP_0_5VDDIO_0_5VOH</a>);</div><div class="line"></div><div class="line">    <span class="comment">/* Set the regulated input buffer trip point multiplier to 1.25 x VRef */</span></div><div class="line">    <a class="code" href="group__group__gpio__functions__sio.html#gae5ec56c5d9eb48cb589d206559e2c7fe">Cy_GPIO_SetVohSel</a>(P0_3_PORT, P0_3_NUM, <a class="code" href="group__group__gpio__sio_voh.html#ga82a402925161b65fee4e301734b4d42e">CY_SIO_VOH_1_25</a>);</div><div class="line"></div><div class="line">    <span class="comment">/* Get the reference voltage of P0.2/P0.3 pair */</span></div><div class="line">    <span class="keywordflow">if</span>(<a class="code" href="group__group__gpio__sio_vref.html#ga7068729049c6c4d4b9a5bc5b35fd5cf8">CY_SIO_VREF_PINREF</a> == <a class="code" href="group__group__gpio__functions__sio.html#ga8f3e4432afbec7485dffe1606dc6233a">Cy_GPIO_GetVrefSel</a>(P0_3_PORT, P0_3_NUM))</div><div class="line">    {</div><div class="line">        <span class="comment">/* Set the reference voltage to 1.2V SRSS internal reference on the P0.2/P0.3 SIO pair */</span></div><div class="line">        <a class="code" href="group__group__gpio__functions__sio.html#gad57f3f01fb4fee362bf8379f265352a5">Cy_GPIO_SetVrefSel</a>(P0_3_PORT, P0_3_NUM, <a class="code" href="group__group__gpio__sio_vref.html#gaa5c0ec7f4e60d65f581e5f6544b76223">CY_SIO_VREF_1_2V</a>);</div><div class="line">    }</div><div class="line"></div></div><!-- fragment --></dd></dl>

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<h2 class="memtitle"><span class="permalink"><a href="#gae5ec56c5d9eb48cb589d206559e2c7fe">&#9670;&nbsp;</a></span>Cy_GPIO_SetVohSel()</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">__STATIC_INLINE void Cy_GPIO_SetVohSel </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_g_p_i_o___p_r_t___type.html">GPIO_PRT_Type</a> *&#160;</td>
          <td class="paramname"><em>base</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">uint32_t&#160;</td>
          <td class="paramname"><em>pinNum</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">uint32_t&#160;</td>
          <td class="paramname"><em>value</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Configures the regulated output reference multiplier for the SIO pin pair. </p>
<p>The regulated output reference controls both the output level of digital output pin and the input trip point of digital input pin in the SIO pair.</p>
<p>Note that this function has no effect on non-SIO pins.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">base</td><td>Pointer to the pin's port register base address</td></tr>
    <tr><td class="paramname">pinNum</td><td>Position of the pin bit-field within the port register</td></tr>
    <tr><td class="paramname">value</td><td>SIO pair reference voltage. Options are detailed in <a class="el" href="group__group__gpio__sio_voh.html">Regulated output voltage level (Voh) and input buffer trip-point of an SIO pair</a> macros</td></tr>
  </table>
  </dd>
</dl>
<dl class="section note"><dt>Note</dt><dd>This function modifies a port register in a read-modify-write operation. It is not thread safe as the resource is shared among multiple pins on a port.</dd></dl>
<dl class="section user"><dt>Function Usage</dt><dd><div class="fragment"><div class="line"></div><div class="line">    <span class="comment">/* Scenario: Assume P0.3 is an SIO pin and that it is paired with P0.2.</span></div><div class="line"><span class="comment">                 Both pins are configured as output pins. The output (driven)</span></div><div class="line"><span class="comment">                 signals on P0.2 and P0.3 need to be at</span></div><div class="line"><span class="comment">                 2.5 x AMuxBusA voltage x 2 for logic high. */</span></div><div class="line"></div><div class="line">    <span class="comment">/* Set the output buffer to be regulated on the P0.2/P0.3 SIO pair */</span></div><div class="line">    <a class="code" href="group__group__gpio__functions__sio.html#ga0d52bed24a328582918b5493c79f10cd">Cy_GPIO_SetVregEn</a>(P0_3_PORT, P0_3_NUM, <a class="code" href="group__group__gpio__sio_vreg.html#ga593d5f4da327d288ca55cadc29aa7c43">CY_SIO_VREG_REGULATED</a>);</div><div class="line"></div><div class="line">    <span class="comment">/* Set the reference voltage to be sourced from AMUXBUS A */</span></div><div class="line">    <a class="code" href="group__group__gpio__functions__sio.html#gad57f3f01fb4fee362bf8379f265352a5">Cy_GPIO_SetVrefSel</a>(P0_3_PORT, P0_3_NUM, <a class="code" href="group__group__gpio__sio_vref.html#gad59e5727b6a9cd54d380502a3f5f8dec">CY_SIO_VREF_AMUX_A</a>);</div><div class="line"></div><div class="line">    <span class="comment">/* Get the regulated voltage multiplier value of P0.2/P0.3 pair */</span></div><div class="line">    <span class="keywordflow">if</span>(<a class="code" href="group__group__gpio__sio_voh.html#ga592ec0db4fe0f78e20090fba46f6e58c">CY_SIO_VOH_1_00</a> == <a class="code" href="group__group__gpio__functions__sio.html#ga304ce3205081a7a29268d3c32bf3b95a">Cy_GPIO_GetVohSel</a>(P0_3_PORT, P0_3_NUM))</div><div class="line">    {</div><div class="line">        <span class="comment">/* Set the regulated voltage multiplier to 2.5 x VRef */</span></div><div class="line">        <a class="code" href="group__group__gpio__functions__sio.html#gae5ec56c5d9eb48cb589d206559e2c7fe">Cy_GPIO_SetVohSel</a>(P0_3_PORT, P0_3_NUM, <a class="code" href="group__group__gpio__sio_voh.html#ga83cc6d63f32f3d4c7a0a6c8c339126d9">CY_SIO_VOH_2_50</a>);</div><div class="line">    }</div><div class="line"></div></div><!-- fragment --></dd></dl>

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<h2 class="memtitle"><span class="permalink"><a href="#ga304ce3205081a7a29268d3c32bf3b95a">&#9670;&nbsp;</a></span>Cy_GPIO_GetVohSel()</h2>

<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">__STATIC_INLINE uint32_t Cy_GPIO_GetVohSel </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_g_p_i_o___p_r_t___type.html">GPIO_PRT_Type</a> *&#160;</td>
          <td class="paramname"><em>base</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">uint32_t&#160;</td>
          <td class="paramname"><em>pinNum</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Returns the regulated output reference multiplier for the SIO pin pair. </p>
<p>Note that this function has no effect on non-SIO pins.</p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramname">base</td><td>Pointer to the pin's port register base address</td></tr>
    <tr><td class="paramname">pinNum</td><td>Position of the pin bit-field within the port register</td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>SIO pair reference voltage. Options are detailed in <a class="el" href="group__group__gpio__sio_voh.html">Regulated output voltage level (Voh) and input buffer trip-point of an SIO pair</a> macros</dd></dl>
<dl class="section user"><dt>Function Usage</dt><dd><div class="fragment"><div class="line"></div><div class="line">    <span class="comment">/* Scenario: Assume P0.3 is an SIO pin and that it is paired with P0.2.</span></div><div class="line"><span class="comment">                 Both pins are configured as output pins. The output (driven)</span></div><div class="line"><span class="comment">                 signals on P0.2 and P0.3 need to be at</span></div><div class="line"><span class="comment">                 2.5 x AMuxBusA voltage x 2 for logic high. */</span></div><div class="line"></div><div class="line">    <span class="comment">/* Set the output buffer to be regulated on the P0.2/P0.3 SIO pair */</span></div><div class="line">    <a class="code" href="group__group__gpio__functions__sio.html#ga0d52bed24a328582918b5493c79f10cd">Cy_GPIO_SetVregEn</a>(P0_3_PORT, P0_3_NUM, <a class="code" href="group__group__gpio__sio_vreg.html#ga593d5f4da327d288ca55cadc29aa7c43">CY_SIO_VREG_REGULATED</a>);</div><div class="line"></div><div class="line">    <span class="comment">/* Set the reference voltage to be sourced from AMUXBUS A */</span></div><div class="line">    <a class="code" href="group__group__gpio__functions__sio.html#gad57f3f01fb4fee362bf8379f265352a5">Cy_GPIO_SetVrefSel</a>(P0_3_PORT, P0_3_NUM, <a class="code" href="group__group__gpio__sio_vref.html#gad59e5727b6a9cd54d380502a3f5f8dec">CY_SIO_VREF_AMUX_A</a>);</div><div class="line"></div><div class="line">    <span class="comment">/* Get the regulated voltage multiplier value of P0.2/P0.3 pair */</span></div><div class="line">    <span class="keywordflow">if</span>(<a class="code" href="group__group__gpio__sio_voh.html#ga592ec0db4fe0f78e20090fba46f6e58c">CY_SIO_VOH_1_00</a> == <a class="code" href="group__group__gpio__functions__sio.html#ga304ce3205081a7a29268d3c32bf3b95a">Cy_GPIO_GetVohSel</a>(P0_3_PORT, P0_3_NUM))</div><div class="line">    {</div><div class="line">        <span class="comment">/* Set the regulated voltage multiplier to 2.5 x VRef */</span></div><div class="line">        <a class="code" href="group__group__gpio__functions__sio.html#gae5ec56c5d9eb48cb589d206559e2c7fe">Cy_GPIO_SetVohSel</a>(P0_3_PORT, P0_3_NUM, <a class="code" href="group__group__gpio__sio_voh.html#ga83cc6d63f32f3d4c7a0a6c8c339126d9">CY_SIO_VOH_2_50</a>);</div><div class="line">    }</div><div class="line"></div></div><!-- fragment --></dd></dl>

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